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Feb 06

Mentor Graphics QuestaSim SE 10.4e


Mentor Graphics QuestaSim SE 10.4e | 1.6 Gb

Mentor Graphics Corporation, a world leader in electronic hardware and software design solutions, providing products and consulting services, has released QuestaSim SE 10.4e, is advanced simulator combines high performance and capacity simulation with unified advanced debug and functional coverage capabilities for the most complete native support of Verilog, SystemVerilog, VHDL, SystemC, SVA, UPF and UVM.

The Questa Advanced Simulator is the core simulation and debug engine of the Questa Verification Solution; the comprehensive advanced verification platform capable of reducing the risk of validating complex FPGA and SoC designs.

New Features Contained in this Release:

– Improved performance and error messages for SystemVerilog TB/OVM/UVM
– Improved performance for VHDL and mixed VHDL/Verilog
– Improved performance for Altera and Xilinx VHDL library components
– New debug support for VHDL dynamic access types
– Native database creation for New Visualizer Debug Environment
– New support for SystemC 2.3
– New coverage auto-save, and other improvements dramatically reducing merge times(VM)
– HTML coverage reporting performance and memory improvements (VM)
– UPF 2.1 support and enhanced Liberty model support (PA)
– Improved Power Aware Simulation capacity and performance (PA) * New PLI Autocompile flow


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